Digital circuits or integrated circuits are commonly used in a variety of different applications. Especially in signal processing applications and other calculation intensive applications there is an ever increasing demand for more computing power and at the same time for reduced power consumption.
In order to provide more computing power in a single integrated circuit the clock frequency or the clock frequencies of the integrated circuit can be increased. An increased clock frequency will result in shorter instruction cycles in e.g. a processor core and will, therefore, allow more computations per time interval.
If the clock frequency of the integrated circuit is increased, special means have to be provided to effectively shield the clock signal paths, for example a slow clock track SCT and a fast clock track FCT. FIG. 6 shows a block diagram of a clock signal path in a common integrated circuit, where a low frequency reference clock SRC is provided to a I/O-Terminal IO of an integrated circuit and forwarded through a buffer BUF and a multiplexer MUX to a phase locked loop, PLL. This PLL generates a high frequency or fast clock signal FCS which is provided to a target logic T through a divider DIV, a multiplexer MUS and a buffer BUF.
FIG. 6 illustrates that there are different points in the signal chain where interferences such as noise N influence the clock signals. Before the low frequency reference clock is provided to the PLL a I/O supply noise and a chip supply noise as well as cross coupling between the different signal lines of the integrated circuit may have an impact on the low frequency reference clock signal. The high frequency clock signal provided by the PLL is then deteriorated by different cross couplings and the chip supply noise N.
If such a high frequency clock signal is to be used in an integrated circuit, it will be typically supplied to different logic units of the integrated circuit. However, in order to supply said high frequency clock signal to the different logic units of the integrated circuit extensive shielding and correction measures have to be provided in the integrated circuit in order to guarantee a failure free transmission of the high frequency clock signal to the different integrated logic units. However, this shielding goes always along with additional circuitry effort.
One option to avoid such a shielding and correction circuitry would be to add a redundant, duplicate circuit of the integrated circuit's PLL which is placed in close proximity to each single logic unit. However, for placing local PLLs near the single logic units the low frequency clock still has to be routed to the single PLLs and shielding and correction measures are still not entirely dispensable. Furthermore, providing local PLLs will increase the overall power consumption of the integrated circuit and require a significant chip area. Hence, this would lead to a more complex and thus expensive integrated circuit which should be avoided in modern design of integrated circuits.